1. Field of the Invention
This invention relates to an improved semiconductor device having a plurality of conductive layers and a method for manufacturing the same. More particularly, this invention relates to a high density multilayer semiconductor device having a plurality of alternately stacked conductive layers and insulating layers, and a method for manufacturing the same.
2. Description of the Prior Art
In recent years, components in a semiconductor device are being made increasingly smaller as IC technology advances, resulting in a greater component density and higher integration of semiconductor devices. An increasing component density presents a problem encountered in multilayer conductor design of the semiconductor device, i.e., that the conductor in an upper layer is broken due to surface depressions or fall-downs caused by an underlying lower conductive layer.
This situation is explained with reference to FIGS. 1A-1C. As shown, the semiconductor device includes a semiconductor substrate 1, the upper or major surface of which is covered with an insulating layer 8. A plurality of transfer gate electrodes 9 are formed spaced apart from one another on the insulating layer 8. An oxide layer 12 is coated on the substrate to cover all of the transfer gate electrodes 9. The oxide layer 12 electrically insulates the transfer gate electrodes 9 comprising a lower conductive layer from an upper conductive layer to be formed on the oxide layer 12. The transfer gate electrodes being of a generally rectangular cross-section, when the metal oxide layer 12 is uniformly applied on the substrate, it plunges or falls down between adjacent gate electrodes forms small pits or depressions. In FIG. 1A, since the lateral distance or gap between the transfer gate electrodes 9 is relatively large, the downward slope of the oxide layer 12 at the surrounding walls of the pits or depressions is rather gentle.
As illustrated in FIG. 1B, the gap between the gate electrodes becomes narrower with an increasing component density in an IC or semiconductor device. With the narrower gaps, an abrupt and steep downward slope is found in the coated oxide layer 12 at the surrounding walls of the pits between the gate electrodes. In addition to the ever diminishing gap, in a transfer gate transistor, a lightly doped drain configuration or LDD structure is an indispensable feature for improving its performance characteristics. In order to realize this LDD structure, it is a common expedient to provide a side wall oxide layer 10 at the opposite sides of each transfer gate electrode 9 as illustrated in FIG. 1C. This addition of the side wall oxide layer 10 contributes to a further reduction in gate-to-gate gap, resulting in even steeper surrounding walls of the depressions. In comparison, while the inter-gate depressions have positively sloped walls in a convex profile in FIG. 1B, the depressions of FIG. 1C have negatively sloped walls in a concave profile. In any case, the presence of such abrupt steps or slopes in the surface of the oxide layer 12 is detrimental in that it may give rise to shorting or breakage in the upper conductive layer to be formed on the oxide layer 12.
One approach to solve this problem of the abrupt slope is to provide an insulating layer of spin-on-glass (hereinafter referred to as SOG) between the upper and lower conductive layers in a multilayer semiconductor device as disclosed in Japanese Patent Laying-Open Gazette No. 102754/1986. An SOG layer is a silicon oxide layer obtained by applying a solution of a silicon compound resolved in an organic solvent such as alcohol in the form of a thin film and evaporating the organic solvent at elevated temperatures.
FIGS. 2A-2D schematically illustrate the process sequence for manufacturing a conventional semiconductor device having multiple conductive layers using the SOG technique.
Referring first to FIG. 2A, there is shown a transfer gate transistor of the type having the lightly doped drain structure. The transistor includes a P-type semiconductor substrate 1 which is covered with an insulating layer 8. A plurality of transfer gate electrodes 9 are formed spaced apart on the insulating layer 8, and a pair of side wall oxide layers 10 are provided on the opposite sides of each transfer gate electrode 9. The semiconductor substrate 1 has an N-type impurity diffusion region 11 formed therein between the electrodes 9. An oxide layer 12 is deposited over the entire substrate, on top of which SOG is spun. The applied SOG is then thermo-set into an SOG layer 13 at a temperature below 800.degree. C. The SOG layer 13 thus formed over the oxide layer 12 effectively fills out the small depression formed in the oxide layer 12 between transfer gate electrodes 9 and provides a relatively smooth surface.
In FIG. 2B, a contact hole 15 is made to extend through the oxide layer 12 and the SOG layer 13 at a location between adjoining transfer gate electrodes 9 by anisotropically etching these insulating layers utilizing photolithography and reactive ion etching (or RIE) techniques. The contact hole 15 is provided for electrically connecting the impurity region 11 in the substrate to an upper conductive layer yet to be formed.
In FIG. 2C, the contact hole 15 thus formed is cleaned. The cleaning is carried out for the purpose of providing an improved and stable contact resistance at the hole. More specifically, in the wake of the previous anisotropic etching, there remain on the wall of the contact hole 15 polymers comprising single-bond or double-bond compounds of carbon and fluorine. In addition, a thin film of oxide is spontaneously grown on the contact hole wall 15. These undesirable polymers and the oxide film are removed from the hole wall by subjecting the contact hole 15 to a wet etching treatment with hydrofluoric acid. But the side effect of this treatment is that the SOG layer 13 is simultaneously and completely etched away since SOG is highly susceptible or sensitive to the etchant used.
In FIG. 2D, in order to form an upper conductive layer, a polysilicon layer 16 and a refractory metal silicide layer 17 are then successively deposited over the oxide layer 12. The polysilicon layer 16 and the silicide layer 17 thus deposited are selectively removed by mask and etch techniques to leave a desired pattern of the upper conductor. It should be noted at this point that the removal of the SOG layer 13 during the previous etching step in no way adversely affects the general configuration or profile of a contact hole 15, so that there is no risk of the polysilicon layer 16 and the silicide layer 17 being broken off at the portion thereof lying within the contact hole 15.
However, there arises a serious problem in a conventional process of manufacturing the semiconductor device described hereinabove. The problem is that the SOG layer 13 deposited on the substrate to obtain a relatively smooth, depression-free upper surface has been entirely removed by the etchant used to clean off the contact hole 15 because of its high susceptibility or sensitivity to the etchant. The complete removal of the SOG layer again exposes the numerous depressions that have been formed in the underlying oxide layer 12. And as previously stated, when the polysilicon layer 16 and the silicide layer 17 which form the upper conductive layer are deposited directly over the oxide layer 12, there are good chances that a breakage of the conductor occurs in this upper conductive layer.